One week Faculty Development Program on FPGA and ASIC design

CoreEL Technologies in collaboration with Xilinx and Mentor conducting “One week Faculty Development Program on FPGA and ASIC design” on 25th Feb – 1st Mar 2019 at Bharathi Vidyapeeth’s College of Engineering, New Delhi.

Last Date of Registration: 24th February 2019

Registration Link: https://goo.gl/forms/QdG110GyIWgRdSHv2