Radar Timing & IO Generation (RTIO) Board

Radar Timing and I/O (RTIO) Generation Board generates all timing and I/O signals required for radar operation. The board features an FPGA based solution implemented to meet the functional requirements of the board.

Read More

Radar Timing & IO Generation (RTIO) Board

Radar Timing and I/O (RTIO) Generation Board generates all timing and I/O signals required for radar operation. The board features an FPGA based solution implemented to meet the functional requirements of the board.

The functional design employs SoC concept, where PowerPC440, a hard macro available in Virtex-5 FXT series of FPGAs is used for communication with the external world via GigE link. Messages are received from the external world over Ethernet, which are decoded by the software application running on the PowerPC440 and appropriate registers are configured in the FPGA. Based on the configured values, RTL logic in the FPGA generates timing signals for various radar sub systems.

The board finds use in airborne radar timing generation and has been adopted across multiple radars

  • Radar Processing Unit
  • Radar Processing Unit-2

KEY FEATURES

  • All timing and I/O pins terminated on the VPX backplane connectors
  • Remote FPGA configuration through Gigabit Ethernet interface
  • FPGA configuration flash programming through JTAG and LAN
  • Linux OS running on PowerPC440 Embedded Processor in the Virtex-5 FPGA
  • SRIO link (x4) capable of running at 3.125 Gbps
  • Health monitoring: Temperature & voltage monitoring of board