Radar Processsing Unit-2

The Radar Processing Unit-2 consists of Digital IF (DIF) receiver boards, Radar Timing and IO generator (RTIO) boards along with signal processing boards. It is built on a custom VPX multi-slot backplane which accommodates the various boards. The entire setup is enclosed in a forced air conduction cooled (FACC) ATR chassis.

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Radar Processsing Unit-2

The Radar Processing Unit-2 is used for airborne radar signal processing and radar timing generation.

The Radar Processing Unit-2 consists of Digital IF (DIF) receiver boards, Radar Timing and IO generator (RTIO) boards along with signal processing boards. It is built on a custom VPX multi-slot backplane which accommodates the various boards. The entire setup is enclosed in a forced air conduction cooled (FACC) ATR chassis. Designed for strength and maximum cooling in a conduction cooled environment, the chassis incorporates brazed folded fin material thermally bonded between the conducting side walls and the outer side panels. The chassis is EMI/EMC compliant to MIL-STD-461E.

The external world IF signals interface with the DIF board on blind-mate RF connectors (BMA-type). All other boards are VPX VITA-46 compliant, which ensures that individual cards are easily replaceable and hence the system maintainability is improved.

The system is used in Active Electronically Scanned Array (AESA) radar. The system receives 8 separate IF channels from external world, which is brought to baseband and then processed by DIF board. This data is then processed by signal processor boards and finally the SBC will generate the video output for display. RTIO receives commands from external world, over Ethernet for generating timing signals. RTIO generates various timing signals to control and configure radar sub modules for various radar modes.

KEY FEATURES

  • 8-slot Air Transport Rack (ATR) chassis
  • Dip brazed fins for efficient heat transfer
  • 8-channel IF receiver inputs
  • System generates and accepts various differential (RS422 and LVDS)
    and single ended (LVTTL) I/Os