Workshop On Signal and Image Processing on Zynq-7000 SoC using Xilinx Vivado Tools

CoreEL Technologies in association with Xilinx and Digilent conducting workshop on “Signal and Image Processing on Zynq-7000 SoC using Xilinx Vivado Tools” on 27th and 28th September 2018, Organized by Department of Electronics & Communication Engineering, PSG Centre for Non-Formal & Continuing Education.

ELIGIBILITY
Faculties from AICTE approved Engineering Colleges with relevant background. Candidates from industries and R & D organizations will also be considered. PG students in related discipline are also eligible.

PRE-REQUISITES

 Digital design experience

 Basic HDL knowledge (VHDL or Verilog)

 System level design experience using Xilinx FPGA

 Basic experience with Xilinx Vivado design software suite

 Good understanding of C programming